Coral NPU's goal is to provide the industry with an NPU reference implementation, based on RISC-V standards, that is easy to adopt and integrate. This approach provides SoC vendors the flexibility to choose their own customized component, such as custom matrix execution unit, alongside Coral NPU's validated IP.
The initial Coral NPU release includes our RISC-V compliant scalar core and vector execution unit. A future release will introduce our RISC-V matrix execution unit, which will provide a complete, end-to-end, open-source stack for a fully RISC-V compliant NPU. Below is a high-level roadmap for planned feature additions and enhancements to the platform:
- Milestone 1 — Full RISC-V compliant scalar core
- Milestone 2 — Full RISC-V compliant vector execution unit
- Milestone 3 — Floating-point and expanded VLEN for LLM support
- Milestone 4 — Full RISC-V compliant matrix execution unit
- Horizon — CHERI (Capability Hardware Enhanced RISC Instructions) and 64-bit support