Platform roadmap

Our goal is to provide the industry with an NPU reference implementation, based on RISC-V standards, that is easy to adopt and integrate.

The initial Coral NPU release included our RISC-V compliant scalar core and the vector execution unit. A future release will introduce the RISC-V matrix execution unit that will provide a complete, end-to-end, open-source stack for a fully RISC-V compliant NPU. Below is a high-level roadmap for planned feature additions and enhancements to the platform.

Note that this roadmap is a tentative plan and is subject to change.

	Milestone 3 Released: Q2 2026	Milestone 4 Released: Q4 2026
Focus	Premier reference accelerator for Gemma	RISC-V VME Matrix execution engine launch Google Coral MLIR compiler release
Highlights	For low-power wearable devices, adding always-on ambient sensing. Neural encoding of sensor data, acts as a trigger for high-power domain or tethered device. Scalar core achieves open standards ISA compliance. Improves the RVV vector execution unit to support larger models and transformer architectures.	For low-power wearable devices, adding always-on ambient sensing. Neural encoding of sensor data, acts as a trigger for high-power domain or tethered device. Scalar core achieves open standards ISA compliance. RISC-V vector execution unit for RVV specification-compliant SIMD. Dedicated quantized outer-product multiply-accumulators (MAC) RISC-V VME ISA extensions for matrix multiplication Open-source Coral MLIR compiler v1.0 on GitHub End-to-end compiler and simulation stack that takes JAX, PyTorch, and LiteRT models straight to the Coral NPU hardware simulator
Specifications	RISC-V 32-bit ISA 4-stage CPU RISC-V RVV vector unit with VLEN = 128, 256, or 512 Supports larger memory capacity, up to 4 GB maximum Supported numerics: int8, int16, FP32 (FP16, BF16) Area = approx. 0.2 mm^2 in TSMC 12nm (N12) Performance = 800 MHz clock x 16 MACs per cycle	RISC-V 32-bit ISA 4-stage CPU RISC-V RVV vector unit with VLEN = 128, 256, or 512 RISC-V VME matrix unit, configurable for up to 1 TOPS and targeting 10mW average power for inference Supports larger memory capacity, up to 4 GB maximum Supported numerics: int8, int16, FP32 (FP16, BF16) Area = approx. 0.2 mm^2 in TSMC 12nm (N12) Performance = 800 MHz clock x 256 MACs per cycle
Reference architectures	Gemma3 270M (LLM) CNNs: Lyra (audio) MobileNet (image)	Gemma3 270M (LLM) CNNs: Lyra (audio) MobileNet (image)
Target model size	Less than 1 GB	Less than 1 GB
Example use cases	Is someone talking Keyword detection Person or object detection Who is the person? What is the object? LLM transcription/translation Token encoding for tethered device	Is someone talking? Keyword detection Person or object detection Who is the person? What is the object? LLM transcription/translation Token encoding for tethered device