Online documentation
The official and most comprehensive reference for the RISC-V Instruction Set Architecture (ISA) is maintained on GitHub by the RISC-V International organization. The main repository for the RISC-V ISA Manual is located here. Use the following links to see the latest posted versions of the unprivileged and privileged reference volumes:
Several useful RISC-V instruction set cheat sheets are also available on GitHub:
Additionally, the following RISC-V documentation repositories on GitHub may be helpful:
- Instruction encodings and related metadata for various RISC-V extensions.
- RISC-V Assembly Programmer's Manual , which complements the ISA specification with information about assembly language programming (PDF downloadable version).
The assembly language programmer's manual typically contains information about:
- Pseudo-instructions: These are assembly-language instructions that are translated by the assembler into one or more actual machine-code instructions. They simplify assembly programming by providing more user-friendly mnemonics.
- Calling conventions: Details on how functions pass arguments, return values, and manage registers on the stack. This is crucial for interoperability between different code modules and languages.
- Assembler directives: Instructions for the assembler itself, controlling aspects like data allocation, section definitions, and symbol visibility.
This resource complements the official RISC-V ISA manuals by providing practical guidance and conventions for writing RISC-V assembly code, bridging the gap between the low-level instruction set and the higher-level task of developing applications.
RISC-V instruction reference basics
The following abbreviations and definitions are used in RISC-V instruction references:
| Item | Description |
|---|---|
XLEN |
32 bits for RV32I (as in Coral NPU) |
rd |
Register, destination |
rs |
Register, source (rs1, rs2) |
imm<N>, off<N> |
Signed immediate (or offset), |
uimm<N> |
Unsigned immediate, |
The base integer (I) instructions have the following format:
opcode[0:6] rd[7:11] funct3[12:14] rs1[15:19] rs2[20:24] or imm[20:31]
The 32-bit instructions are aligned on 32-bit boundaries in memory. Word size is defined as follows:
| Word size | # of bits |
|---|---|
| halfword | 16 bits |
| word | 32 bits |
| doubleword | 64 bits |
| quadword | 128 bits |