Simulators

Overview

Instruction-level simulators allow users to simulate the Coral NPU processor and test their software without the need for physical hardware. The Coral NPU simulators can be used for system modeling, compiler validation, and software development.

There are two simulators for Coral NPU:

  • Behavioral simulator called MPACT-CoralNPU
  • Cycle-accurate, Verilog-based simulator for exact hardware performance emulation (rvv_core_mini_axi_sim)

The cycle-accurate simulator is available from the Google Coral NPU repository on GitHub.

Use the Verilog-based simulator to obtain precise, accurate results—exactly as would be seen on the Coral NPU hardware. You must model your system memories correctly to achieve this. This simulator is clock-cycle-accurate and so you are able to see what signals actually toggle by using the waveform generation option.

The cycle-exact simulator executes slowly, however, and so if all you need is functional equivalence then use the MPACT-Coral NPU simulator. The MPACT-CoralNPU simulator is much faster and so is ideal for early experimentation and software development.

Both tools facilitate simulation-based ML system testing, optimization, and benchmarking. The cycle-accurate simulator is the tool to use for hardware development and debugging.

MPACT-CoralNPU supports scalar, floating-point, and vector instruction sets.

Google provides the simulator open-source files on GitHub so that users who are extending the Coral NPU hardware IP can also modify and build the simulators themselves.

Both Coral NPU simulators accept two input file formats: .elf (Executable and Linkable Format) and .bin (binary). The .elf files contain extra information that is helpful in debugging, while flattened .bin files are smaller. Fully compiled .elf files are generally preferred for simulation due to their flexibility with memory configurations and debugging data.

ELF file format for simulation

An .elf file is a standard binary file format used to load and execute software on embedded processors within a hardware simulator. It packages the compiled code, data, and metadata needed for the simulation to function correctly.

The ELF format is the standard binary format used for executables, object code, and shared libraries in most Unix-based systems, including Linux and BSD.

An .elf file provides the initial state for the processor's memory. When the simulation starts, the hardware's internal memory (block RAM) is loaded with the code and data from the .elf file.

The ELF format allows the file to incorporate debugging information—specifically, symbol tables that map the machine code back to the original source code. This allows a debugger to help you troubleshoot your code during simulation by setting breakpoints and inspecting variables.

The common workflow when using .elf files in hardware simulation is:

  • Software compilation: Write and compile the source code using a cross-compiler that targets the specific processor in your hardware design. The output is an .elf file.
  • Adding the .elf to the project: Add the generated .elf file to your hardware project, often within an integrated design environment (IDE).
  • Associating the .elf: Link the .elf file to a specific processor instance in your hardware design.
  • Simulation: Run the hardware simulation. The simulator loads the contents of the .elf file into the simulated memory of the processor.
  • Debugging: Using the debugging tools in your IDE, you can interact with the running simulation, stepping through your software and hardware execution in a coordinated manner.

Using the cycle-exact RVV simulator

To get started using the cycle-exact Coral NPU simulator, first complete the setup steps given in Software prerequisites and system setup.

To build the RVV simulator executable from the source files, enter this command:
bazel build //tests/verilator_sim:rvv_core_mini_axi_sim

To start the simulator, enter:
bazel-bin/tests/verilator_sim/rvv_core_mini_axi_sim --binary program

To see a list of the command-line options (flags) available, use the –helpfull option:
bazel-bin/tests/verilator_sim/rvv_core_mini_axi_sim --helpfull

Option Description
--binary ELF or BIN binary program to execute
--cycles Simulation cycles; default = 100000000
--debug_axi Enable AXI traffic debugging; default = false
--instr_trace Log instructions to console; default = false
--trace Dump VCD trace; default = false
--helpfull Show these options

Co-simulation

Co-simulation involves running the same program on both a cycle-accurate simulator (UVM testbench) and a functional Instruction Set Simulator (ISS) simultaneously to ensure consistent behavior. The concurrent simulations are run in lock-step.

Coral NPU implements a RISC-V Verification Interface (RVVI) to collect retired instructions in every cycle. The results are compared to the functional MPACT-CoralNPU instruction simulator to ensure that Coral NPU aligns with the RISC-V specification.

The MPACT-CoralNPU ISS co-simulation module can also be reused to verify other RISC-V cores equipped with an RVVI interface.