Architecture basics

  • Coral NPU functions as an AXI4/TileLink peripheral within a System-on-Chip, using an LSU memory interface for data transfers between processor cores and memory.

  • It includes standard RISC-V microcontroller features such as instruction decoding, pipelining with hazard detection, exception handling, scalar core instructions, and interrupt handling.

  • The NPU utilizes the AXI4 bus interface for connecting to the SoC, supporting address validity, data integrity, handshake protocols, burst transactions, and error signaling.

  • Coral NPU implements RISC-V standard control and status registers, accessible via specific instructions for atomic read-modify-write operations.

Overview

Coral NPU is designed to be an AXI4/TileLink peripheral in a System-on-Chip (SoC). Using the AXI bus, Coral’s Load-Store Unit (LSU) memory interface handles data transfers between the processor core and the memory system. The LSU is shared between the scalar core and vector core. It handles memory requests, including loads (reading data) and stores (writing data), and communicates with the memory via specific signals and protocols.

RISC-V microcontroller features

The Coral NPU IP provides the following RISC-V standard microcontroller features and operations:

  • Instruction decoding and control logic
  • Instruction pipeline
    • Hazard detection logic (RAW, WAR, WAW)
    • Pipeline stall mechanisms
    • Pipeline flush mechanisms
    • Instruction scoreboard
  • Exception detection and handling
    • Exception entry and exit sequences
    • Exception cause recording
    • Exception prioritization
  • Scalar core instructions
    • Arithmetic: add, subtract, multiply, divide, etc.
    • Load/store data with various address modes (immediate, register, indexed)
  • Scalar core branch instructions (BEQ, BNE, BLT, BGE, JAL, JALR, etc.)
  • Scalar core interrupt handling
  • Control and status registers
    • Access permissions for different registers (read-only, write-only, read-write)
  • Load-store unit (LSU)
    • Read and write operations to ITCM, DTCM, and external memories via IBUS, DBUS, EBUS
    • Different data sizes: byte, half-word, word
    • Different burst modes and burst lengths for memory transactions
    • Handles back-pressure on WRESP (write response) and RDATA (read data) signals

AXI4 bus interface

The Coral NPU IP uses the industry-standard AXI4 Advanced Microcontroller Bus Architecture (AMBA) to connect the system to the encompassing SoC.

AXI4 is an open-standard, on-chip interconnect specification for the connection and management of functional blocks in SoC designs. AXI4 simplifies the development of silicon systems with multiple processors and large numbers of controllers and peripherals. You can find the AMBA AXI4 specification here.

On Coral NPU, the AXI4 bus and interconnect provides the following:

  • Address validity and alignment
  • Data integrity (write data, read data)
  • Handshake protocols (ready/valid)
  • Burst transactions (INCR, FIXED)
  • Error signaling
  • AXI4 interface signals (AW, W, B, AR, R channels)

Control and status registers (CSRs)

Coral NPU implements the RISC-V standard control and status registers, following the rv32_Zicsr specification. The RISC-V standard CSRs are accessed by using special instructions. For example, the CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the register, zero-extends the value to XLEN bits, and writes it to integer register rd.

All CSR instructions atomically read-modify-write a single CSR, where the CSR specifier is encoded in the csr field of the instruction.

All of the RISC-V Zicsr standard CSRs are defined in the RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Chapter 2 Control and Status Registers.

Key concepts and instructions for the RISC-V CSRs include:

  • Separate address space for up to 4,096 registers for each hardware thread (hart)
  • Atomic read-modify-write instructions, for example:
    • CSRRW (Atomic Read/Write CSR)
    • CSRRS (Atomic Read and Set Bits in CSR)
    • CSRRC (Atomic Read and Clear Bits in CSR)
  • Immediate variants of the CSR instructions:
    • CSRRWI
    • CSRRSI
    • CSRRCI
  • Assembler pseudo-instructions for common CSR operations, such as reading (CSRR), writing (CSRW), setting bits (CSRS), and clearing bits (CSRC)

By convention, the upper 4 bits of the CSR address (csr[11:8]) are used to encode the read and write accessibility of the CSRs. The top two bits (csr[11:10]) indicate whether the register is read/write (00, 01, or 10) or read-only (11). The next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR.

While CSRs are primarily associated with the RISC-V privileged architecture and machine-mode operations, the Zicsr instructions are available at different privilege levels for various purposes:

  • Privileged architecture: Used by an operating system or hypervisor to manage the system, handle interrupts, and control hardware features.
  • Unprivileged code: Provides access to a subset of CSRs, most commonly performance counters, timers, and floating-point status registers.

Coral NPU custom CSRs

The Coral NPU processor has three unique, non-RISC-V control/status registers. These registers are intended to be read or written from outside Coral NPU, for example by the system's host processor.

Note that these CSRs are separate from the RISC-V Zicsr standard registers.

RESET_CONTROL

  • Offset: 0x0
  • Description: Controls reset and clock gating for the Coral NPU core. On power-up, the core is held in reset with its clock gated. To start the core, the clock gate must be released first, followed by de-asserting reset.
Bits Name Description Access Reset Value
0 RESET When 1, the core is held in reset. When 0, the core is not in reset. R/W 1
1 CLOCK_GATE When 1, the core's clock is gated. When 0, the core's clock is running. R/W 1
31:2 RESERVED Reserved, writes ignored, reads return 0. R 0

PC_START

  • Offset: 0x4
  • Description: Sets the program counter for the Coral NPU core. This should be programmed before releasing the core from reset.
Bits Name Description Access Reset Value
31:0 START_ADDRESS The address where the core will begin execution. R/W 0

STATUS

  • Offset: 0x8
  • Description: Provides status of the Coral NPU core. This is a read-only register.
Bits Name Description Access Reset Value
0 HALTED When 1, the core has halted (e.g. after an mpause instruction). R 0
1 FAULT When 1, the core has encountered a fault. R 0
31:2 RESERVED Reserved, reads return 0. R 0