Architecture basics

Overview

Coral NPU is designed to be an AXI4/TileLink peripheral in a System-on-Chip (SoC). Using the AXI bus, Coral’s Load-Store Unit (LSU) memory interface handles data transfers between the processor core and the memory system. The LSU is shared between the scalar core and vector core. It handles memory requests, including loads (reading data) and stores (writing data), and communicates with the memory via specific signals and protocols.

RISC-V microcontroller features

The Coral NPU IP provides the following RISC-V standard microcontroller features and operations:

  • Instruction decoding and control logic
  • Instruction pipeline
    • Hazard detection logic (RAW, WAR, WAW)
    • Pipeline stall mechanisms
    • Pipeline flush mechanisms
    • Instruction scoreboard
  • Exception detection and handling
    • Exception entry and exit sequences
    • Exception cause recording
    • Exception prioritization
  • Scalar core instructions
    • Arithmetic: add, subtract, multiply, divide, etc.
    • Load/store data with various address modes (immediate, register, indexed)
  • Scalar core branch instructions (BEQ, BNE, BLT, BGE, JAL, JALR, etc.)
  • Scalar core interrupt handling
  • Control and status registers
    • Access permissions for different registers (read-only, write-only, read-write)
  • Load-store unit (LSU)
    • Read and write operations to ITCM, DTCM, and external memories via IBUS, DBUS, EBUS
    • Different data sizes: byte, half-word, word
    • Different burst modes and burst lengths for memory transactions
    • Handles back-pressure on WRESP (write response) and RDATA (read data) signals

AXI4 bus interface

The Coral NPU IP uses the industry-standard AXI4 Advanced Microcontroller Bus Architecture (AMBA) to connect the system to the encompassing SoC.

AXI4 is an open-standard, on-chip interconnect specification for the connection and management of functional blocks in SoC designs. AXI4 simplifies the development of silicon systems with multiple processors and large numbers of controllers and peripherals. You can find the AMBA AXI4 specification here.

On Coral NPU, the AXI4 bus and interconnect provides the following:

  • Address validity and alignment
  • Data integrity (write data, read data)
  • Handshake protocols (ready/valid)
  • Burst transactions (INCR, FIXED)
  • Error signaling
  • AXI4 interface signals (AW, W, B, AR, R channels)

Control and status registers (CSRs)

Coral NPU implements the RISC-V standard control and status registers, following the rv32_Zicsr specification. RISC-V defines a separate address space for the CSRs.

There are specific instructions for accessing the registers. All CSR instructions atomically read-modify-write a single CSR, where the CSR specifier is encoded in the csr field of the instruction.