Starboard Module Reference: cpu_features.h
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Structs
SbCPUFeatures
Members
SbCPUFeaturesArchitecture architecture
Architecture of the processor.
const char * brand
Processor brand string retrievable by CPUID or from /proc/cpuinfo under the
key "model name" or "Processor".
int32_t icache_line_size
Processor cache line size in bytes of Level 1 instruction cache and data
cache. Queried by sysconf(_SC_LEVEL1_ICACHE_LINESIZE) and
sysconf(_SC_LEVEL1_DCACHE_LINESIZE), or from files /proc/cpuinfo,
/proc/self/auxv, or CPUID with CLFLUSH instruction.
int32_t dcache_line_size
bool has_fpu
Processor has floating-point unit on-chip.
uint32_t hwcap
Bit-mask containing processor features flags. Queried by getauxval(AT_HWCAP)
if it is supported.
uint32_t hwcap2
Similar to hwcap. Queried by getauxval(AT_HWCAP2) if it is supported.
SbCPUFeaturesARM arm
Processor features specific to each architecture. Set the appropriate
SbCPUFeatures<ARCH_NAME> for the underlying architecture. Set the other
SbCPUFeatures<OTHER_ARCH> to be invalid, meaning:
'-1' for signed integer fields
'false' for feature flag fields
'0' for feature flag bitmasks
empty string for string fields
SbCPUFeaturesMIPS mips_arch
The reason that the "_arch" suffix exists for mips is because on some
platforms that use MIPS as the underlying architecture, "mips" is already
defined as a macro.
SbCPUFeaturesX86 x86
SbCPUFeaturesARM
Members
int16_t implementer
Processor implementer/implementor code. ARM is 0x41, NVIDIA is 0x4e, etc.
int16_t variant
Processor variant number, indicating the major revision number.
int16_t revision
Processor revision number, indicating the minor revision number.
int16_t architecture_generation
Processor architecture generation number, indicating the generations
(ARMv6-M, ARMv7, etc) within an architecture family. This field is called
"Architecture" or "Constant" in the processor ID register.
int16_t part
Processor part number, indicating Cortex-M0, Cortex-A8, etc.
bool has_neon
ARM Advanced SIMD (NEON) vector instruction set extension.
bool has_thumb2
Thumb-2 mode.
bool has_vfp
VFP (SIMD vector floating point instructions).
bool has_vfp3
VFP version 3
bool has_vfp4
VFP version 4
bool has_vfp3_d32
VFP version 3 with 32 D-registers.
bool has_idiva
SDIV and UDIV hardware division in ARM mode.
bool has_aes
Arm 64 feature flags
AES instructions.
bool has_crc32
CRC32 instructions.
bool has_sha1
SHA-1 instructions.
bool has_sha2
SHA-256 instructions.
bool has_pmull
64-bit PMULL and PMULL2 instructions.
SbCPUFeaturesMIPS
Members
SbCPUFeaturesX86
Members
const char * vendor
Processor vendor ID string, e.g. "GenuineIntel", "AuthenticAMD", etc
int16_t family
Processor family ID
int16_t ext_family
Processor extended family ID, needs to be examined only when the family ID
is 0FH.
int16_t model
Processor model ID
int16_t ext_model
Processor extended model ID, needs to be examined only when the family ID is
06H or 0FH.
int16_t stepping
Processor stepping ID, a product revision number
int16_t type
Processor type ID
int32_t signature
A raw form of collection of processor stepping, model, and family
information
bool has_cmov
Conditional Move Instructions (plus FCMOVcc, FCOMI with FPU).
bool has_mmx
Multimedia extensions.
bool has_sse
SSE (Streaming SIMD Extensions).
bool has_sse2
SSE2 extensions.
bool has_tsc
Time Stamp Counter.
bool has_sse3
SSE3 extensions.
bool has_pclmulqdq
PCLMULQDQ instruction.
bool has_ssse3
Supplemental SSE3 extensions.
bool has_sse41
SSE-4.1 extensions.
bool has_sse42
SSE-4.2 extensions.
bool has_movbe
MOVBE instruction.
bool has_popcnt
POPCNT instruction.
bool has_osxsave
XSAVE/XRSTOR/XGETBV/XSETBV instruction enabled in this OS.
bool has_avx
AVX (Advanced Vector Extensions).
bool has_f16c
16-bit FP conversions.
bool has_fma3
Fused multiply-add.
bool has_aesni
AES new instructions (AES-NI).
bool has_avx2
AVX2 Extensions.
bool has_avx512f
AVX-512 Foundation.
bool has_avx512dq
AVX-512 DQ (Double/Quad granular) Instructions.
bool has_avx512ifma
AVX-512 Integer Fused Multiply-Add instructions.
bool has_avx512pf
AVX-512 Prefetch.
bool has_avx512er
AVX-512 Exponential and Reciprocal.
bool has_avx512cd
AVX-512 Conflict Detection.
bool has_avx512bw
AVX-512 BW (Byte/Word granular) Instructions.
bool has_avx512vl
AVX-512 VL (128/256 Vector Length) Extensions.
bool has_bmi1
First group of bit manipulation extensions.
bool has_bmi2
Second group of bit manipulation extensions.
bool has_lzcnt
Bit manipulation instruction LZCNT.
bool has_sahf
SAHF in long mode.
Functions
SbCPUFeaturesGet
Retrieve the underlying CPU features and place it in features, which must not
be NULL.
If this function returns false, it means the CPU architecture is unknown and all
fields in features are invalid.
Declaration
bool SbCPUFeaturesGet(SbCPUFeatures *features)
Except as otherwise noted, the content of this page is licensed under the Creative Commons Attribution 4.0 License, and code samples are licensed under the Apache 2.0 License. For details, see the Google Developers Site Policies. Java is a registered trademark of Oracle and/or its affiliates.
Last updated 2025-09-03 UTC.
[[["Easy to understand","easyToUnderstand","thumb-up"],["Solved my problem","solvedMyProblem","thumb-up"],["Other","otherUp","thumb-up"]],[["Missing the information I need","missingTheInformationINeed","thumb-down"],["Too complicated / too many steps","tooComplicatedTooManySteps","thumb-down"],["Out of date","outOfDate","thumb-down"],["Samples / code issue","samplesCodeIssue","thumb-down"],["Other","otherDown","thumb-down"]],["Last updated 2025-09-03 UTC."],[[["\u003cp\u003eThe content describes the \u003ccode\u003eSbCPUFeatures\u003c/code\u003e struct and its nested structs (\u003ccode\u003eSbCPUFeaturesARM\u003c/code\u003e, \u003ccode\u003eSbCPUFeaturesMIPS\u003c/code\u003e, \u003ccode\u003eSbCPUFeaturesX86\u003c/code\u003e), which hold detailed information about CPU architecture, features, and capabilities.\u003c/p\u003e\n"],["\u003cp\u003e\u003ccode\u003eSbCPUFeatures\u003c/code\u003e contains fields like processor brand, cache line sizes, hardware capability bitmasks, and architecture-specific details.\u003c/p\u003e\n"],["\u003cp\u003eEach architecture-specific struct (\u003ccode\u003eSbCPUFeaturesARM\u003c/code\u003e, \u003ccode\u003eSbCPUFeaturesMIPS\u003c/code\u003e, \u003ccode\u003eSbCPUFeaturesX86\u003c/code\u003e) has members that identify the processor's manufacturer, model, and supported instruction sets, such as NEON, AES, AVX, and SSE.\u003c/p\u003e\n"],["\u003cp\u003eThe \u003ccode\u003eSbCPUFeaturesGet\u003c/code\u003e function retrieves CPU features and populates an \u003ccode\u003eSbCPUFeatures\u003c/code\u003e struct, returning false if the CPU architecture is unknown and the struct is invalid.\u003c/p\u003e\n"]]],["The core content details the `SbCPUFeatures` struct and its architecture-specific substructs (`SbCPUFeaturesARM`, `SbCPUFeaturesMIPS`, `SbCPUFeaturesX86`), which store information about CPU features. This includes the processor's architecture, brand, cache line sizes, floating-point unit presence, and feature bitmasks. Each architecture struct contains fields for specific characteristics, like implementer, part number, and instruction set extensions. The `SbCPUFeaturesGet` function retrieves this CPU information and populates a provided `SbCPUFeatures` struct; returning false if the architecture is unknown.\n"],null,["Structs\n\nSbCPUFeatures\n\nMembers\n\n- `SbCPUFeaturesArchitecture architecture`\n\n Architecture of the processor.\n- `const char * brand`\n\n Processor brand string retrievable by CPUID or from /proc/cpuinfo under the\n key \"model name\" or \"Processor\".\n- `int32_t icache_line_size`\n\n Processor cache line size in bytes of Level 1 instruction cache and data\n cache. Queried by sysconf(_SC_LEVEL1_ICACHE_LINESIZE) and\n sysconf(_SC_LEVEL1_DCACHE_LINESIZE), or from files /proc/cpuinfo,\n /proc/self/auxv, or CPUID with CLFLUSH instruction.\n- `int32_t dcache_line_size`\n\n- `bool has_fpu`\n\n Processor has floating-point unit on-chip.\n- `uint32_t hwcap`\n\n Bit-mask containing processor features flags. Queried by getauxval(AT_HWCAP)\n if it is supported.\n- `uint32_t hwcap2`\n\n Similar to hwcap. Queried by getauxval(AT_HWCAP2) if it is supported.\n- `SbCPUFeaturesARM arm`\n\n Processor features specific to each architecture. Set the appropriate\n `SbCPUFeatures\u003cARCH_NAME\u003e` for the underlying architecture. Set the other\n `SbCPUFeatures\u003cOTHER_ARCH\u003e` to be invalid, meaning:\n - '-1' for signed integer fields\n\n - 'false' for feature flag fields\n\n - '0' for feature flag bitmasks\n\n - empty string for string fields\n\n- `SbCPUFeaturesMIPS mips_arch`\n\n The reason that the \"_arch\" suffix exists for mips is because on some\n platforms that use MIPS as the underlying architecture, \"mips\" is already\n defined as a macro.\n- `SbCPUFeaturesX86 x86`\n\nSbCPUFeaturesARM\n\nMembers\n\n- `int16_t implementer`\n\n Processor implementer/implementor code. ARM is 0x41, NVIDIA is 0x4e, etc.\n- `int16_t variant`\n\n Processor variant number, indicating the major revision number.\n- `int16_t revision`\n\n Processor revision number, indicating the minor revision number.\n- `int16_t architecture_generation`\n\n Processor architecture generation number, indicating the generations\n (ARMv6-M, ARMv7, etc) within an architecture family. This field is called\n \"Architecture\" or \"Constant\" in the processor ID register.\n- `int16_t part`\n\n Processor part number, indicating Cortex-M0, Cortex-A8, etc.\n- `bool has_neon`\n\n ARM Advanced SIMD (NEON) vector instruction set extension.\n- `bool has_thumb2`\n\n Thumb-2 mode.\n- `bool has_vfp`\n\n VFP (SIMD vector floating point instructions).\n- `bool has_vfp3`\n\n VFP version 3\n- `bool has_vfp4`\n\n VFP version 4\n- `bool has_vfp3_d32`\n\n VFP version 3 with 32 D-registers.\n- `bool has_idiva`\n\n SDIV and UDIV hardware division in ARM mode.\n- `bool has_aes`\n\n Arm 64 feature flags\n\n AES instructions.\n- `bool has_crc32`\n\n CRC32 instructions.\n- `bool has_sha1`\n\n SHA-1 instructions.\n- `bool has_sha2`\n\n SHA-256 instructions.\n- `bool has_pmull`\n\n 64-bit PMULL and PMULL2 instructions.\n\nSbCPUFeaturesMIPS\n\nMembers\n\n- `bool has_msa`\n\n MIPS SIMD Architecture (MSA).\n\nSbCPUFeaturesX86\n\nMembers\n\n- `const char * vendor`\n\n Processor vendor ID string, e.g. \"GenuineIntel\", \"AuthenticAMD\", etc\n- `int16_t family`\n\n Processor family ID\n- `int16_t ext_family`\n\n Processor extended family ID, needs to be examined only when the family ID\n is 0FH.\n- `int16_t model`\n\n Processor model ID\n- `int16_t ext_model`\n\n Processor extended model ID, needs to be examined only when the family ID is\n 06H or 0FH.\n- `int16_t stepping`\n\n Processor stepping ID, a product revision number\n- `int16_t type`\n\n Processor type ID\n- `int32_t signature`\n\n A raw form of collection of processor stepping, model, and family\n information\n- `bool has_cmov`\n\n Conditional Move Instructions (plus FCMOVcc, FCOMI with FPU).\n- `bool has_mmx`\n\n Multimedia extensions.\n- `bool has_sse`\n\n SSE (Streaming SIMD Extensions).\n- `bool has_sse2`\n\n SSE2 extensions.\n- `bool has_tsc`\n\n Time Stamp Counter.\n- `bool has_sse3`\n\n SSE3 extensions.\n- `bool has_pclmulqdq`\n\n PCLMULQDQ instruction.\n- `bool has_ssse3`\n\n Supplemental SSE3 extensions.\n- `bool has_sse41`\n\n SSE-4.1 extensions.\n- `bool has_sse42`\n\n SSE-4.2 extensions.\n- `bool has_movbe`\n\n MOVBE instruction.\n- `bool has_popcnt`\n\n POPCNT instruction.\n- `bool has_osxsave`\n\n XSAVE/XRSTOR/XGETBV/XSETBV instruction enabled in this OS.\n- `bool has_avx`\n\n AVX (Advanced Vector Extensions).\n- `bool has_f16c`\n\n 16-bit FP conversions.\n- `bool has_fma3`\n\n Fused multiply-add.\n- `bool has_aesni`\n\n AES new instructions (AES-NI).\n- `bool has_avx2`\n\n AVX2 Extensions.\n- `bool has_avx512f`\n\n AVX-512 Foundation.\n- `bool has_avx512dq`\n\n AVX-512 DQ (Double/Quad granular) Instructions.\n- `bool has_avx512ifma`\n\n AVX-512 Integer Fused Multiply-Add instructions.\n- `bool has_avx512pf`\n\n AVX-512 Prefetch.\n- `bool has_avx512er`\n\n AVX-512 Exponential and Reciprocal.\n- `bool has_avx512cd`\n\n AVX-512 Conflict Detection.\n- `bool has_avx512bw`\n\n AVX-512 BW (Byte/Word granular) Instructions.\n- `bool has_avx512vl`\n\n AVX-512 VL (128/256 Vector Length) Extensions.\n- `bool has_bmi1`\n\n First group of bit manipulation extensions.\n- `bool has_bmi2`\n\n Second group of bit manipulation extensions.\n- `bool has_lzcnt`\n\n Bit manipulation instruction LZCNT.\n- `bool has_sahf`\n\n SAHF in long mode.\n\nFunctions\n\nSbCPUFeaturesGet\n\nRetrieve the underlying CPU features and place it in `features`, which must not\nbe NULL.\n\nIf this function returns false, it means the CPU architecture is unknown and all\nfields in `features` are invalid.\n\nDeclaration \n\n bool SbCPUFeaturesGet(SbCPUFeatures *features)"]]
