Open source projects to accelerate silicon design.
High Level Synthesis (HLS) toolchain which produces synthesizable designs from flexible, high-level descriptions of functionality.
Automated RTL to GDSII flow that performs full ASIC implementation steps from RTL all the way down to GDSII.
Bazel rules for Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc).