Introduction to MPACT-Sim
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MPACT-Sim is a framework and library designed to make it easier to create
high performance ISA simulators for a wide range of instruction set
architectures. Simulators built using MPACT-Sim are easy to create, easy to
instrument, and fast. The motivating use-case for MPACT-Sim is to quickly
create, and easily modify, simulators for (instruction set) architectural
exploration. However, the resulting simulator can also be used for system
modeling, compiler validation, or software development for architectures that
have no (or limited) hardware availability.
MPACT-Sim makes it easy to express and implement instruction semantics as simple
C++ functions/callables. MPACT-Sim also provides a declarative methodology for
expressing instructions to enable automatic generation of most of the
instruction decoder, increasing the ease and velocity by which new simulators
can be created. Custom configuration entries can easily be added, and the
resulting simulators are easy to instrument using a set of standard classes.
Tutorials
The tutorials that follow provide a guided walk-through of creating an ISA
simulator for a subset of RiscV instructions sufficient for executing a "hello
world" application compiled for the RV32I architectural subset. They cover
the following activities:
Write an ISA decoder description for RV32I.
This describes the individual
instructions independent of their external representation (encoding). This
description is used to generate C++ code that initializes the simulator's
internal instruction descriptors.
Write a binary decoder description for RV32I.
This describes the binary
encoding of the instructions, bit-fields and their values. This is used to
generate a decoder for the instructions capable of mapping an instruction word
to an opcode, and extracting the values of specific bit-fields.
Write an integrated (full) instruction decoder that integrates the two
generated decoders, adding required code to cover what the generated code does
not.
Write instruction semantic functions to provide the implementations of each
of the target RV32I instructions.
Writing the remaining code required to complete the simulator, including the
code controlling instruction issue, is not covered by the current tutorials, but
may be added in the future. However, sample code can be viewed in the tutorial
repository, as well as in the repository for full
[MPACT-RiscV simulator]https://github.com/mpact-riscv).
The simulator infrastructure is written in C++, so a good working knowledge of
C++ is assumed.
Except as otherwise noted, the content of this page is licensed under the Creative Commons Attribution 4.0 License, and code samples are licensed under the Apache 2.0 License. For details, see the Google Developers Site Policies. Java is a registered trademark of Oracle and/or its affiliates.
Last updated 2024-06-26 UTC.
[[["Easy to understand","easyToUnderstand","thumb-up"],["Solved my problem","solvedMyProblem","thumb-up"],["Other","otherUp","thumb-up"]],[["Missing the information I need","missingTheInformationINeed","thumb-down"],["Too complicated / too many steps","tooComplicatedTooManySteps","thumb-down"],["Out of date","outOfDate","thumb-down"],["Samples / code issue","samplesCodeIssue","thumb-down"],["Other","otherDown","thumb-down"]],["Last updated 2024-06-26 UTC."],[[["\u003cp\u003eMPACT-Sim is a framework and library for building high-performance instruction set architecture (ISA) simulators.\u003c/p\u003e\n"],["\u003cp\u003eIt simplifies simulator creation and modification, making it ideal for architectural exploration, system modeling, and software development.\u003c/p\u003e\n"],["\u003cp\u003eMPACT-Sim uses C++ functions to define instruction semantics and provides a declarative approach for instruction decoding, speeding up simulator development.\u003c/p\u003e\n"],["\u003cp\u003eThe provided tutorials guide users through creating a basic RISC-V simulator, covering instruction decoding and semantic function implementation.\u003c/p\u003e\n"],["\u003cp\u003eWhile instruction issue and control are not explicitly covered in the tutorials, examples are available in the provided repository links.\u003c/p\u003e\n"]]],[],null,["# Introduction to MPACT-Sim\n\nMPACT-Sim is a framework and library designed to make it easier to create\nhigh performance ISA simulators for a wide range of instruction set\narchitectures. Simulators built using MPACT-Sim are easy to create, easy to\ninstrument, and fast. The motivating use-case for MPACT-Sim is to quickly\ncreate, and easily modify, simulators for (instruction set) architectural\nexploration. However, the resulting simulator can also be used for system\nmodeling, compiler validation, or software development for architectures that\nhave no (or limited) hardware availability.\n\nMPACT-Sim makes it easy to express and implement instruction semantics as simple\nC++ functions/callables. MPACT-Sim also provides a declarative methodology for\nexpressing instructions to enable automatic generation of most of the\ninstruction decoder, increasing the ease and velocity by which new simulators\ncan be created. Custom configuration entries can easily be added, and the\nresulting simulators are easy to instrument using a set of standard classes.\n\nTutorials\n---------\n\nThe tutorials that follow provide a guided walk-through of creating an ISA\nsimulator for a subset of RiscV instructions sufficient for executing a \"hello\nworld\" application compiled for the RV32I architectural subset. They cover\nthe following activities:\n\n- Write an ISA decoder description for RV32I.\n\n This describes the individual\n instructions independent of their external representation (encoding). This\n description is used to generate C++ code that initializes the simulator's\n internal instruction descriptors.\n- Write a binary decoder description for RV32I.\n\n This describes the binary\n encoding of the instructions, bit-fields and their values. This is used to\n generate a decoder for the instructions capable of mapping an instruction word\n to an opcode, and extracting the values of specific bit-fields.\n- Write an integrated (full) instruction decoder that integrates the two\n generated decoders, adding required code to cover what the generated code does\n not.\n\n- Write instruction semantic functions to provide the implementations of each\n of the target RV32I instructions.\n\nWriting the remaining code required to complete the simulator, including the\ncode controlling instruction issue, is not covered by the current tutorials, but\nmay be added in the future. However, sample code can be viewed in the tutorial\nrepository, as well as in the repository for full\n\\[MPACT-RiscV simulator\\]https://github.com/mpact-riscv).\n\nThe simulator infrastructure is written in C++, so a good working knowledge of\nC++ is assumed."]]